Building in reliability with latch-up, ESD and hot carrier effects on 0.25 μm CMOS technology

Microelectronics Reliability

Volumn 38, Issue 10, 1998, Pages 1547-1552

  Leroux, C ^a   Salome, P ^a   Reimbold, G ^a   Blachier, D ^a   Guegan, G ^a   Bonis, M ^b  

^a CEA LETI   (France)

^b ORANGE LABS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0038367182     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(98)00057-2     Document Type: Article

References (7)

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3. Leroux C, Guegan G, Lerme M. Process and design considerations for latch-up optimisation. ESSDERC 93, Grenoble, France. 1993:197-200.
4. Amerasekera A, Abeelen W, Roozendaal L, Hannemann M, Schofield P. ESD failure modes: characteristics, mechanisms and process influences. IEEE Transactions on Elec Devices 1992;39:430-6.
5. Standard MIL STD 883C notice 8 method 3015-7, 1989:1811-16.
6. Verhaege K, Luchies JM, Russ C, Groseneken G, Kuper F. NMOS transistor behaviour under CDM stress conditions and relation to other stress models. ESREF 95, Arcachon, France, 1995:117-25.
7. Salome P, Leroux C, Chante JP, Crevel P, Reimbold G. Study of a 3D phenomenon during ESD stresses in deep submicron CMOS technologies using photon emission tool. IEEE, IRPS 97, Denver, U.S.A., 1997:325-23.