A transition-encoded dynamic bus technique for high-performance interconnects

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 16-17

  Anders, Mark ^a   Rai, Nivruti ^a   Krishnamurthy, Ram ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENT CONTROL; FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; PERFORMANCE;

DOMINO REPEATER; DROP-IN REPLACEMENT; INTERCONNECT DELAY REDUCTION; TRANSITION-ENCODED DYNAMIC BUS TECHNIQUE;

INTERCONNECTION NETWORKS;

EID: 0242695815     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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2. M. T. Bohr, 1995 IEDM Proc., pp. 241-244.
3. M. R. Stan, et. al., IEEE Tran. VLSI 5, #4 pp. 444-454.
4. S. Tyagi et. al., 2000 IEDM Tech. Digest, pp. 567-570.
5. D. Sager et. al., 2001 ISSCC, pp. 324-325.