Fabrication of self-aligned 90-nm fully depleted SOI CMOS SLOTFETs

IEEE Electron Device Letters

Volumn 22, Issue 7, 2001, Pages 345-347

  Chen, C K ^a   Chen, C L ^a   Gouker, P M ^a   Wyatt, P W ^a   Yost, D R ^a   Burns, J A ^a   Suntharalingan, V ^a   Fritze, M ^a   Keast, C L ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

CMOS; MOSFETs; SOI technology

Indexed keywords

ELECTRIC INSULATORS; ELECTRIC VARIABLES MEASUREMENT; INTEGRATED CIRCUIT MANUFACTURE; MOSFET DEVICES; PERFORMANCE; PHOTOLITHOGRAPHY; POLYSILICON; SILICON ON INSULATOR TECHNOLOGY;

DOPANT ACTIVATION ANNEAL CYCLE; NITRIDE SPACER TECHNOLOGY; RING OSCILLATOR PROPAGATION DELAY; SOURCE DRAIN REGION;

CMOS INTEGRATED CIRCUITS;

EID: 0035397828     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.930686     Document Type: Article

References (5)

1. SOI and device scaling
2. Recessed-channel structure for fabrication ultrathin SOI MOSFET with low series resistance
3. Low resistance Ti or Co salicided raised source-drain transistors
4. Thin silicide development for fully-depleted SOI CMOS technology
5. Design of 25-nm SALVO PMOS devices