Differences in the sub-processes of ultra fine pitch stencil printing due to type-6 and type-7 Pb-free solder pastes used for flip chip

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2003, Pages 536-543

  Jackson, G J ^a   Hendriksen, M W ^b   Durairaj, R K ^a   Ekere, N N ^a   Desmulliez, M P Y ^c   Kay, R W ^c  

^a UNIVERSITY OF GREENWICH   (United Kingdom)

^b Celestica Limited   (United Kingdom)

^c HERIOT WATT UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

FLIP CHIP DEVICES; LEAD ALLOYS; PARTICLE SIZE ANALYSIS; PRINTING; RHEOLOGY; SCANNING ELECTRON MICROSCOPY; SELF ASSEMBLY; SOLDERING ALLOYS; VISCOSITY;

LEAD-FREE SOLDER PASTE; SOLDER PASTE PRINTING; STENCIL FABRICATION METHOD; ULTRA FINE PITCH STENCIL PRINTING;

ELECTRONICS PACKAGING;

EID: 0038350868     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. Suhir, E, "Microelectronics and Photonics - the future", Microelectronics Journal, Vol. 31, Issue 11-12, 2000, pp.839-851.
2. Tummala, R, White, G, Sundaram, V, "SOP:Microelectronics Systems Packaging Technology for 21st Century; Prospects and Progress", Proc 12th IMAPS European Microelectronics & Packaging Conference, Harrogate, UK, Jun 1999, pp.327-335.
3. Hendriksen, M.W, Frimpong, F.F, Ekere, N.N, "Interconnect Solutions for Advanced Area Array Packaging", Journal of Microelectronics International, Volume 16, Number 2, (Apr.1999), pp.49.
4. Lau, J.H. Low Cost Flip Chip Assembly, McGraw-Hill (New York, 1995).
5. B. Huang, N-C. Lee, 'Solder bumping via paste reflow for area array packages', Proceedings IEMT, SEMICON West 2002, San Jose, CA USA (July 2002) pp1-17.
6. T.A. Nguty, B. Salam, R. Durairaj, N.N Ekere, 'Understanding the process window for printing lead-free solder pastes', IEEE Trans. Elect. Pack. Manufacturing, Vol24, No. 4, (October 2001).
7. R. Durairaj, G.J. Jackson, N.N. Ekere, G. Glinski, C. Bailey, 'Correlation of solder paste rheology with computational simulations of the stencil printing process', Soldering and Surface Mount Technology, Vol. 14 No. 1 (2002).
8. J. H. Lau, 'Solder joint reliability', Van Nostrand Reinhold (New York 1991).
9. D. Manessis, R. Patzelt, S. Nieland; A. Ostmann, R. Aschenbrenner, H. Reichl, 'Technical challenges of stencil printing technology for ultra fine pitch flip chip bumping', proceedings International Symposium on Microelectronics, Denver, Colorado (2002) pp727.
10. X. Bao, N.-C. Lee, R. B. Raj, K.P. Rangen, A. Maria, 'Engineering solder paste performance through controlled stress rheology analysis', Soldering and surface Mount Technology, 10/2 (1998) pp26-35.
11. T. A. Nguty, N. N. Ekere, A. Adebayo, 'Correlating Solder paste Composition with Stencil Printing Performance', Proceedings - 1999 IEEE/CPMT Int't Electronics Manufacturing Technology Symposium, Austin TX (October 18-19 1999) pp 304-309.
12. V. G. Kolli, F. Gadala-Maria, R. Anderson, 'Rheological Characterisation of Solder Pastes for Surface Mount Applications', IEEE Transactions On Components, Packaging, And Manufacturing Technology - Part B, Vol. 20, No. 4 (November 1997) pp 416-423.
13. P.N. Houston, J. Bentley, B. J. Lewis, B. A. Smith, D. Baldwin, 'Processing strategies for high speed 0201 implementation', Proc. IEMT, San Jose CA, 2002.