Advances in fine pitch lead free assembly process

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2003, Pages 834-839

  Doraiswami, Ravi ^b   Sankararaman, Sandeep ^b   Kim, Woopoung ^b   Li, Jing ^b   Zhang, Zhuqing ^b   Gupta, Piyush ^b   Nakanishi, Kensuke ^a   Borkar, Manish ^b   Madhavan, Raghav ^b   Govind, Vinu ^b   Choi, Suna ^b   Aggarwal, Ankur O ^b   Sun, Y ^b   Fan, Lianhua ^b   Sundaram, Venky ^b   Swminathan, Madhayan ^b   Wong, C P ^b   Tummala, Rao R ^b  

^a Harima Chemicals Inc   (Japan)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIELECTRIC LOSSES; ELECTRIC CONDUCTIVITY OF SOLIDS; ELECTRONICS PACKAGING; FLIP CHIP DEVICES; INTEGRATED CIRCUIT LAYOUT; LEAD; MATHEMATICAL MODELS; PASSIVATION; POLYIMIDES; RELIABILITY; WAVEGUIDES;

BUMPING MATERIAL; FINE PITCH LEAD FREE ASSEMBLY PROCESS; LEAD FREE SOLDER; PARASITIC; SOLDER BUMPING PROCESS; UNDER BUMP METALLURGY;

SOLDERING;

EID: 0038350607     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. ITRS Roadmap 1999.
2. Solberg, V.; Light,D.; Fjelstad,J, "Reliable and Low cost Wafer Level Packaging. Process Description and Qualification Testing Results for Wide Area Vertical Expansion (WAVE ™) Package Technology," Electronics Manufacturing Technology Symposium, 2000. Twenty-Sixth IEEE/CPMT International, 2000, pp. 108-114
3. Guo-Wei Xiao; Chan, P.C.H.; Teng, A.; Jian Cai; Yuen, M.M.F, "Effect of Cu stud microstructure and electroplating process on intermetallic compounds growth and reliability of flip-chip solder bump," IEEE Transactions on Components, Packaging and Manufacturing Technology, Part A: Packaging Technologies, Volume: 24 Issue: 4, Dec 2001, pp. 682-690.
4. Frank Stepniak, "Conversion of under bump metallurgy into intermetallics: the impact on flip-chip reliability;" Microelectronics Reliability; vol.41, no.5, May 2001, pp. 735-44.
5. Jong-kai Lin, Treliant Fang and Rajiv Bajaj, "Squeegee Bump Technology", Proceedings of the 50th Electronics and component technology conference, 2000 pp 46-53.
6. Plating technology for electronics packaging, Hideo Honma, Electrochimica Acta, 47, 2001, pp 75-84
7. F. Nakano, T. Soga, and S. Amagi, "Resin Insertion Effect on Thermal Cycle Resistivity of Flip-Chip Mounted LSI Devices", Proceedings of International Society of Hybrid Microelectronics Conference, 1987, pp 536.
8. D. Suryanarayana, R. Hsiao, T. P. Gall, and J. M. McCreary, "Flip-Chip Solder Bimp Fatigue Life Enhanced by Polymer Encapsulation", Proceedings of IEEE 40th ECTC, 1990, pp 338.
9. S. Han and K. K. Wang, "Analysis of the Flow of Encapsulant During Underfill Encapsulation of Flip-Chips", IEEE Trans. On CPMT, Part B, Vol. 20(4), 1997, pp 424.
10. S.H. Shi, T. Yamashita, and C.P. Wong, "Development of the Wafer-Level Compressive-Flow Underfill Process and Its Required Materials", Proceedings of the 49th Electronic Components and Technology Conference, 1999, pp. 961.
11. R.B. Marks, "A Multiline Method of Network Analyzer Calibration," IEEE Trans. Microwave Theory and Techniques, vol. 39, Jul. 1991, pp. 1205-1215
12. M. Lee and S. Nam, "An Accurate Broadband Measurement of Substrate Dielectric Constant," IEEE Microwave and Guided Wave Letters., vol. 6, Apr. 1996, pp 168-170.
13. D. F. Williams, U. Arz, and H. Grabinski, "Accurate Characteristic Impedance Measurement on Silicon," IEEE MTT-Symposium Digest, 1998, pp 1917-1920.
14. S. Vandengerghe, et al., "Characteristic Impedance Extraction using Calibration Comparison," IEEE Trans. Microwave Theory and Techniques, vol. 49, Dec. 2001, pp 2573-2579.