Reduced dynamic swing domino logic

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 2003, Pages 33-36

  Mader, Roy ^a   Kourtev, Ivan ^a  

^a University of Pittsburgh   (United States)

Author keywords

Design; Measurement; Performance

Indexed keywords

CAPACITANCE; DIGITAL CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); LOGIC CIRCUITS; LOGIC DESIGN; SPURIOUS SIGNAL NOISE; THRESHOLD VOLTAGE;

DYNAMIC DOMINO LOGIC CIRCUITS; NOISE TOLERANCE;

VLSI CIRCUITS;

EID: 0038037544     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/764813.764817     Document Type: Conference Paper

References (9)

1. S.-O. Jung, K.-W. Kim, and S.-M. Kang, "Low-swing clock domino logic incorporating dual supply and dual threshold voltages," Proceedings of the 39th conference on Design automation, pp. 467-472, ACM Press, 2002.
2. V. Kursun and E. G. Friedman, "Low swing dual threshold voltage domino logic," Proceedings of the 12 th ACM Symposium on Great Lakes Symposium on VLSI, pp. 47-52, ACM Press, 2002.
3. S.-J. Shieh and J.-S. Wang, "Design of low-power domino circuits using multiple supply voltages," The 8th IEEE International Conference on Electronics, Circuits and Systems, Vol. 2, pp. 711-714, 2001.
4. M. Casu, "Reduced clock swing domino logic," Electronic Letters, Vol.38, Iss.16, pp. 860-861, 2002.
5. B. Ramasubramanian, H. Schmit, and L.R. Carley, "Mixed-swing quadrail for low power dual-rail domino logic," Proceedings 1999 international symposium on Low power electronics and design, pp. 82-84, ACM Press, 1999.
6. L. Rave, A. Carley, "Mixed-swing methodology for domino logic circuits," IEEE Conference on Custom Integrated Circuits, pp. 85-88, 2001.
7. O. Rjoub, A. Koufopavlou, "Multiple low swing voltage values for CPL, CVSL and domino logic families," The 7th IEEE International Conference on Electronics, Circuits and Systems, Vol. 2, pp. 903-906, 2000.
8. A. Rjoub, O. Koufopavlou, and S. Nikolaidis, "Low-power/low-swing domino CMOS logic," Proceedings of the 1998 IEEE International Circuits and Systems, ISCAS, pp. 13-16, 1998.
9. A. Alvandpour, R. Krishnamurthy, and K. Soumyanath, "A sub-130-nm conditional keeper technique," IEEE Journal of Solid-State Circuits, Vol. 37, pp. 633-638, 2002.