Deep submicron CMOS technology using top-edge round STI and dual gate oxide for low power 256 M-bit mobile DRAM

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 42, Issue 4 B, 2003, Pages 1892-1896

  Lee, Chihoon ^a,b   Park, Donggun ^b   Jo, Namhyuk ^b   Hwang, Chanseong ^b   Joon Kim, Hyeong ^a   Lee, Wonshik ^b  

^a Seoul National University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

Corner round; Dual gate oxide; Low power; Mobile DRAM; STI; Undercut

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC CONDUCTIVITY OF SOLIDS; GATES (TRANSISTOR); INTERFACES (MATERIALS); LEAKAGE CURRENTS; OXIDATION; SEMICONDUCTING BORON; SILICA; SILICON WAFERS; SUBSTRATES; THRESHOLD VOLTAGE;

DUAL GATE OXIDE; GATE INDUCED DRAIN LEAKAGE CURRENT; SHALLOW TRENCH ISOLATION; SINGLE GATE OXIDE;

MOSFET DEVICES;

EID: 0038010035     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.42.1892     Document Type: Article

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