Congestion-driven placement improvement algorithm for large scale sea-of-gates arrays

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1997, Pages 573-576

  Sadakane, Toshiyuki ^a   Shirota, Hiroshi ^a   Takahashi, Kazuhiro ^a   Terai, Masayuki ^a   Okazaki, Kaoru ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; LOGIC DESIGN; LOGIC GATES; SIMULATED ANNEALING;

GAIN ESTIMATION METHOD; SEA OF GATE (SOG) ARRAYS;

CELLULAR ARRAYS;

EID: 0030720393     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)