Error diagnosis for transistor-level verification

Proceedings - Design Automation Conference

Volumn , Issue , 1994, Pages 218-224

  Kuehlmann, Andreas ^a   Cheng, David I ^a   Srinivasan, Arvind ^a   LaPotin, David P ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; BOOLEAN FUNCTIONS; CMOS INTEGRATED CIRCUITS; CODING ERRORS; COMPUTER DEBUGGING; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; ERROR CORRECTION; PROBABILITY; SET THEORY;

BINARY DECISION DIAGRAM; ERROR DIAGNOSIS; FORMAL VERIFICATION TECHNIQUES;

ERROR DETECTION;

EID: 0028592997     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/196244.196358     Document Type: Conference Paper

References (13)