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Volumn 38, Issue 2, 2003, Pages 303-311

A 0.5-V power-supply scheme for low-power system LSIs using multi-Vth SOI CMOS technology

Author keywords

0.5 V power supply scheme; Buck dc dc converter; Flip flop with sleep function; Level converter; Multi Vth; SOI

Indexed keywords

DIGITAL TO ANALOG CONVERSION; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; STANDBY POWER SERVICE; THRESHOLD VOLTAGE;

EID: 0037319647     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.807406     Document Type: Article
Times cited : (16)

References (14)
  • 2
    • 0033280874 scopus 로고    scopus 로고
    • 0.18μm metal gate fully depleted SOI MOSFETs for advanced CMOS applications
    • June
    • J. Chen et al., "0.18μm metal gate fully depleted SOI MOSFETs for advanced CMOS applications," in Symp. VLSI Technology Dig. Tech. Papers, June 1999, pp. 25-26.
    • (1999) Symp. VLSI Technology Dig. Tech. Papers , pp. 25-26
    • Chen, J.1
  • 3
    • 0031095651 scopus 로고    scopus 로고
    • An ultralow-voltage SOI CMOS pass-gate logic
    • Mar.
    • T. Fuse et al., "An ultralow-voltage SOI CMOS pass-gate logic," IEICE Trans. Electron., vol. E80-C, no. 3, pp. 472-477, Mar. 1997.
    • (1997) IEICE Trans. Electron. , vol.E80-C , Issue.3 , pp. 472-477
    • Fuse, T.1
  • 4
    • 0031073501 scopus 로고    scopus 로고
    • A 0.5-V 200-MHz 1-stage 32-b ALU using a body bias controlled SOI pass-gate logic
    • Feb.
    • T. Fuse et al., "A 0.5-V 200-MHz 1-stage 32-b ALU using a body bias controlled SOI pass-gate logic," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1997, pp. 286-287.
    • (1997) IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers , pp. 286-287
    • Fuse, T.1
  • 5
    • 0031706869 scopus 로고    scopus 로고
    • 0.5V 320 MHz 8b multiplexer/demultiplexer chips based on a gate array with regular-structured DTMOS/SOI
    • Feb.
    • T. Hirota et al., "0.5V 320MHz 8b multiplexer/demultiplexer chips based on a gate array with regular-structured DTMOS/SOI," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1998, pp. 188-189.
    • (1998) IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers , pp. 188-189
    • Hirota, T.1
  • 6
    • 0032669133 scopus 로고    scopus 로고
    • Dynamic threshold pass-transistor logic for improved delay at lower power supply voltage
    • Jan.
    • N. Lindert et al., "Dynamic threshold pass-transistor logic for improved delay at lower power supply voltage," IEEE J. Solid-State Circuits, vol. 34, pp. 85-89, Jan. 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.34 , pp. 85-89
    • Lindert, N.1
  • 7
    • 0034784883 scopus 로고    scopus 로고
    • A 0.5-V power-supply scheme for low power LSIs using multi-Vt SOI CMOS technology
    • June
    • T. Fuse et al., "A 0.5-V power-supply scheme for low power LSIs using multi-Vt SOI CMOS technology," in Symp. VLSI Circuits Dig. Tech. Papers, June 2001, pp. 219-220.
    • (2001) Symp. VLSI Circuits Dig. Tech. Papers , pp. 219-220
    • Fuse, T.1
  • 8
    • 0032023709 scopus 로고    scopus 로고
    • Variable supply-voltage scheme for low-power high-speed CMOS digital design
    • Mar.
    • T. Kuroda et al., "Variable supply-voltage scheme for low-power high-speed CMOS digital design," IEEE J. Solid-State Circuits, vol. 33, pp. 454-462, Mar. 1998.
    • (1998) IEEE J. Solid-State Circuits , vol.33 , pp. 454-462
    • Kuroda, T.1
  • 9
    • 0013277474 scopus 로고    scopus 로고
    • An on-chip high-efficiency and low-noise DC/DC converter using divided switches with current control technique
    • Feb.
    • S. Sakiyama et al., "An on-chip high-efficiency and low-noise DC/DC converter using divided switches with current control technique," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1999, pp. 156-157.
    • (1999) IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers , pp. 156-157
    • Sakiyama, S.1
  • 10
    • 0031162017 scopus 로고    scopus 로고
    • A 1-V high-speed MTCMOS circuit scheme for power-down application circuits
    • June
    • S. Shigematsu et al., "A 1-V high-speed MTCMOS circuit scheme for power-down application circuits," IEEE J. Solid-State Circuits, vol. 32, pp. 861-869, June 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , pp. 861-869
    • Shigematsu, S.1
  • 11
    • 0029715111 scopus 로고    scopus 로고
    • A low-power data holding circuit with an intermittent power supply scheme for sub-1-V MT-CMOS LSIs
    • June
    • H. Akamatsu et al., "A low-power data holding circuit with an intermittent power supply scheme for sub-1-V MT-CMOS LSIs," in Symp. VLSI Circuits Dig. Tech. Papers, June 1996, pp. 14-15.
    • (1996) Symp. VLSI Circuits Dig. Tech. Papers , pp. 14-15
    • Akamatsu, H.1
  • 12
    • 0027575799 scopus 로고
    • Sub-1-V swing internal bus architecture for future low-power ULSIs
    • Apr.
    • Y. Nakagome et al., "Sub-1-V swing internal bus architecture for future low-power ULSIs," IEEE J. Solid-State Circuits, vol. 28, pp. 414-419, Apr. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , pp. 414-419
    • Nakagome, Y.1
  • 13
    • 0033714415 scopus 로고    scopus 로고
    • Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIs
    • June
    • Y. Kanno et al., "Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIs," in Symp. VLSI Circuits Dig. Tech. Papers, June 2000, pp. 202-203.
    • (2000) Symp. VLSI Circuits Dig. Tech. Papers , pp. 202-203
    • Kanno, Y.1
  • 14
    • 0035172530 scopus 로고    scopus 로고
    • 300-Mb/s level converters for 0.5-V system LSIs using FD/PD-SOI technology
    • Oct.
    • T. Fuse et al., "300-Mb/s level converters for 0.5-V system LSIs using FD/PD-SOI technology," in Proc. IEEE Int. SOI Conf., Oct. 2001, pp. 79-80.
    • (2001) Proc. IEEE Int. SOI Conf. , pp. 79-80
    • Fuse, T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.