0.5 V 320 MHz 8 b multiplexer/demultiplexer chips based on a gate array with regular-structured DTMOS/SOI

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 188-189,-435

  Hirota, Takanori ^a   Ueda, Kimio ^a   Wada, Yoshiki ^a   Mashiko, Koichiro ^a   Hamano, Hisanori ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DIVIDING CIRCUITS (ARITHMETIC); FLIP FLOP CIRCUITS; GATES (TRANSISTOR); MICROPROCESSOR CHIPS; MOSFET DEVICES; MULTIPLEXING EQUIPMENT; NAND CIRCUITS; SILICON ON INSULATOR TECHNOLOGY;

SEPARATION BY IMPLANTATION OF OXYGEN (SIMOX);

CMOS INTEGRATED CIRCUITS;

EID: 0031706869     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)