Booth multiplier accepting both a redundant or a non redundant input with no additional delay

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2000, Pages 205-214

  Daumas, Marc ^a   Matula, David W ^a  

^a UNIVERSITÉ DE LYON   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; BINARY CODES; CMOS INTEGRATED CIRCUITS; COMPUTER CIRCUITS; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; ENCODING (SYMBOLS); LOGIC CIRCUITS; LOGIC DESIGN; MULTIPLYING CIRCUITS; REDUNDANCY;

BOOTH MULTIPLIER; BOOTH RECODING; CRITICAL PATH DELAY;

CARRY LOGIC;

EID: 0033716117     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)