Fast on-chip inductance simulation using a precorrected-FFT method

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 1, 2003, Pages 49-66

  Hu, Haitian ^a,b   Blaauw, David T ^c   Zolotov, Vladimir ^b   Gala, Kaushik ^c   Zhao, Min ^c   Panda, Rajendran ^c   Sapatnekar, Sachin S ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

^b MOTOROLA INC   (United States)

^c UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Circuit simulation; Electrostatic analysis; Inductance; Interconnect; Magnetic interaction; Model order reduction

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTROSTATICS; FAST FOURIER TRANSFORMS; MATRIX ALGEBRA; OPTIMIZATION; PROBLEM SOLVING; VECTORS;

CIRCUIT SIMULATION;

INDUCTANCE;

EID: 0037230578     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.805719     Document Type: Article

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