Parametric time delay modeling for floating point units

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4791, Issue , 2002, Pages 448-455

  Fahmy, Hossam A H ^a   Liddicoat, Albert A ^a   Flynn, Michael J ^a  

^a Stanford University   (United States)

Author keywords

Floating point adders; Redundancy; Signed digits; Time delay modeling

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; DIGITAL ARITHMETIC; LOGIC DESIGN; LOGIC GATES; REDUNDANCY;

FLOATING POINT ADDERS; SIGNED DIGITS; TIME DELAY MODELING;

ADDERS;

EID: 0036992572     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.452014     Document Type: Conference Paper

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