Improving the effectiveness of floating point arithmetic

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 1, Issue , 2001, Pages 875-879

  Fahmy, Hossam A H ^a   Liddicoat, Albert A ^a   Flynn, Michael J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; DIVIDING CIRCUITS (ARITHMETIC); MULTIPLYING CIRCUITS; NUMBER THEORY;

ARITHMETIC UNITS; CARRY FREE ARITHMETIC OPERATIONS; REDUNDANT NUMBER SYSTEM;

DIGITAL ARITHMETIC;

EID: 0035573133     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/acssc.2001.987049     Document Type: Conference Paper

References (14)

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6. Reducing the latency of floating-point arithmetic operations
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9. Reducing the mean latency of floating-point addition
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11. How many logic levels does floating-point addition require?
12. TM microprocessor
13. High-performance floating point divide
14. High-performance arithmetic for division and the elementary functions