A genetic testing framework for digital integrated circuits

Proceedings of the International Conference on Tools with Artificial Intelligence

Volumn , Issue , 2002, Pages 521-526

  Yu, Xiaoming ^a   Fin, Alessandro ^b   Fummi, Franco ^b   Rudnick, Elizabeth M ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b UNIVERSITY OF VERONA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

C (PROGRAMMING LANGUAGE); COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; DIGITAL INTEGRATED CIRCUITS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC GATES; PROGRAM TRANSLATORS;

FAULT COVERAGE; GATE LEVEL TEST GENERATION; GENETIC TESTING; REGISTER TRANSFER LEVEL;

GENETIC ALGORITHMS;

EID: 0036920348     PISSN: 10636730     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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