A highly cost efficient 8F2 DRAM cell with a double gate vertical transistor device for 100 nm and beyond

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 415-418

  Weis, R ^a   Hummler, K ^a   Akatsu, H ^a   Kudelka, S ^a   Dyer, T ^a   Seitz, M ^a   Scholz, A ^a   Kim, B ^a   Wise, M ^a   Malik, R ^a   Strane, J ^a   Goebel, Th ^a   McStay, K ^a   Beintner, J ^a   Arnold, N ^a   Gerber, R ^a   Liegl, B ^a   Knorr, A ^a   Economikos, L ^a   Simpson, A ^a   Yan, W ^a   Dobuzinsky, D ^a   Mandelman, J ^a   Nesbit, L ^a   Radens, C J ^a   Divakaruni, R ^a   Bergner, W ^a   Bronner, G ^a   Mueller, W ^a   more..

^a INFINEON TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITOR STORAGE; DESIGN FOR TESTABILITY; DYNAMIC RANDOM ACCESS STORAGE; GATES (TRANSISTOR); LITHOGRAPHY; MASKS; NANOTECHNOLOGY; SEMICONDUCTOR STORAGE;

DOUBLE GATE VERTICAL TRANSISTOR; TRENCH CAPACITOR;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 17644443254     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)