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Volumn 2001-January, Issue , 2001, Pages 629-634

RPack: Routability-driven packing for cluster-based FPGAs

Author keywords

Clustering methods; Computer science; Cost function; Design automation; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Logic circuits; Routing; Table lookup

Indexed keywords

AUTOMATION; CLUSTER ANALYSIS; COMPUTER SCIENCE; COST FUNCTIONS; COSTS; DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT INTERCONNECTS; LOGIC CIRCUITS; LOGIC DESIGN; TABLE LOOKUP;

EID: 84949800774     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913379     Document Type: Conference Paper
Times cited : (56)

References (10)
  • 1
    • 0033723235 scopus 로고    scopus 로고
    • The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density
    • Feb
    • E. Ahmed, J. Rose, "The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density," ACM/SIGDA International Symposium on FPGA, pp. 3-12, Feb 2000.
    • (2000) ACM/SIGDA International Symposium on FPGA , pp. 3-12
    • Ahmed, E.1    Rose, J.2
  • 3
    • 0032659075 scopus 로고    scopus 로고
    • Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density
    • Feb
    • A. Marquardt, V. Betz, J. Rose, "Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density," ACM/SIGDA International Symposium on FPGAs, pp.37-46, Feb.1999.
    • (1999) ACM/SIGDA International Symposium on FPGAs , pp. 37-46
    • Marquardt, A.1    Betz, V.2    Rose, J.3
  • 6
    • 0028341924 scopus 로고
    • Routability-Driven Technology Mapping for Lookup Table-Based FPGAs
    • Jan
    • M. Schlag, J. Kong, P. K. Chan, "Routability-Driven Technology Mapping for Lookup Table-Based FPGAs," IEEE Transactions on CAD, Vol. 13, pp.13-26, Jan 1994.
    • (1994) IEEE Transactions on CAD , vol.13 , pp. 13-26
    • Schlag, M.1    Kong, J.2    Chan, P.K.3
  • 8
    • 0028259317 scopus 로고
    • FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Design
    • Jan
    • J. Cong, Y. Ding, "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Design," IEEE Trans. on Computer-Aided Design. Vol.13, No.1, pp. 1-12,Jan. 1994.
    • (1994) IEEE Trans. on Computer-Aided Design , vol.13 , Issue.1 , pp. 1-12
    • Cong, J.1    Ding, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.