Test point insertion based on path tracing

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1996, Pages 2-8

  Touba, Nur A ^a   McCluskey, Edward J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; CONTROLLABILITY; FAILURE ANALYSIS; LOGIC GATES; OBSERVABILITY; RANDOM PROCESSES; SIGNAL THEORY;

CIRCUIT UNDER TEST; PATH TRACING; TEST POINT INSERTION;

INTEGRATED CIRCUIT TESTING;

EID: 0029718599     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)