Test synthesis of systems-on-a-chip

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 10, 2002, Pages 1211-1217

  Ravi, Srivaths ^a   Jha, Niraj K ^b  

^a NEC LABORATORIES AMERICA   (United States)

^b Princeton University   (United States)

Author keywords

Design for testability; Synthesis for testability; System on a chip; Test synthesis

Indexed keywords

ALGORITHMS; DESIGN FOR TESTABILITY; ELECTRIC NETWORK SYNTHESIS; EMBEDDED SYSTEMS; FINITE AUTOMATA; MICROPROCESSOR CHIPS; OPTIMIZATION;

SYNTHESIS FOR TESTABILITY; SYSTEMS-ON-A-CHIP;

INTEGRATED CIRCUIT TESTING;

EID: 0036811866     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.802265     Document Type: Article

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