High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 10, 2002, Pages 1318-1325

  Tanzawa, Toru ^a   Takano, Yoshinori ^a   Watanabe, Kentaro ^a   Atsumi, Shigeru ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Channel erase; Flash memories; High voltage generator; High voltage transistor; Level shifter; Ripple voltage; Scaling

Indexed keywords

COUPLED CIRCUITS; ELECTRIC BREAKDOWN; FLASH MEMORY; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; LOGIC GATES; VOLTAGE CONTROL;

CHANNEL ERASE; HIGH-VOLTAGE TRANSISTOR; LEVEL SHIFTER; RIPPLE VOLTAGE;

TRANSISTORS;

EID: 0036773123     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.803045     Document Type: Article

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