A channel-erasing 1.8V-only 32Mb NOR flash EEPROM with a bit-line direct-sensing scheme

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 276-277

  Atsumi, S ^a   Umezawa, A ^a   Tanzawa, T ^a   Taura, T ^a   Shiga, H ^a   Takano, Y ^a   Miyaba, T ^a   Matsui, M ^a   Watanabe, H ^a   Isobe, K ^a   Kitamura, S ^a   Yamada, S ^a   Saito, M ^a   Mori, S ^a   Watanabe, T ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; DECODING; MICROPROCESSOR CHIPS; THRESHOLD VOLTAGE;

BLOCK DECODER CIRCUITS;

FLASH MEMORY;

EID: 0034428240     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. 2 Ti-salicided STI Cell technology for high-density NOR flash memories and high performance embedded application
2. A 2.7V only 8Mb ×16 NOR flash memory
3. Optimization of word-line booster circuits for low-voltage flash memories
4. A sampling weak-program method to tighten Vth-distribution of 0.5V for low-voltage flash memories