A three-valued D-flip-flop and shift register using multiple-junction surface tunnel transistors

IEEE Transactions on Electron Devices

Volumn 49, Issue 8, 2002, Pages 1336-1340

  Uemura, Tetsuya ^a   Baba, Toshio ^b  

^a HOKKAIDO UNIVERSITY   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

D FF; Multiple valued logic; NDR; Shift register; Tunnel transistor

Indexed keywords

ELECTRIC CURRENT MEASUREMENT; FLIP FLOP CIRCUITS; MOSFET DEVICES; SEMICONDUCTING INDIUM GALLIUM ARSENIDE; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR JUNCTIONS; SEQUENTIAL CIRCUITS; SHIFT REGISTERS; SWITCHING FUNCTIONS; THRESHOLD VOLTAGE; TUNNEL JUNCTIONS;

DRAIN CURRENT; LATCHING FUNCTION; MULTIPLE JUNCTION SURFACE TUNNEL TRANSISTORS; MULTIPLE VALUED LOGIC;

TRANSISTORS;

EID: 0036684669     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2002.801431     Document Type: Article

References (11)

1. Resonant tunneling device with multiple negative differential resistance: Digital and signal applications with reduced circuit complexity
2. Resonant tunneling diode and HEMT logic circuits with multiple threshold and multilevel output
3. Multi-valued decoder based on resonant tunneling diodes in current tapping mode
4. Multiple-junction surface tunnel transistors for multiple-valued logic circuits
5. Development of InGaAs-based multiple-junction surface tunnel transistors for multiple-valued logic circuits
6. Development of quantum functional devices for multiple-valued logic circuits
7. Demonstration of a novel multiple-valued T-gate using multiple-junction surface tunnel transistors and its application to three-valued data flip-flop
8. Three-terminal silicon surface junction tunneling device for room temperature operation
9. Current-voltage characteristics of high current density silicon esaki diodes grown by molecular beam epitaxy and the influence of thermal annealing
10. Epitaxially gwown Si/SiGe interband tunneling diodes with high room-temperature peak-to-valley ratio