Development of InGaAs-based multiple-junction surface tunnel transistors for multiple-valued logic circuits

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 1998, Pages 7-12

  Baba, Toshio ^a   Uemura, Tetsuya ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT DENSITY; ELECTRIC INVERTERS; LOGIC GATES; MANY VALUED LOGICS; NAND CIRCUITS; NEGATIVE RESISTANCE; SEMICONDUCTING INDIUM COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; TUNNEL JUNCTIONS;

MULTIPLE JUNCTION SURFACE TUNNEL TRANSISTORS (MJ STT); PEAK TO VALLEY RATIO (PVR);

TRANSISTORS;

EID: 0031626229     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)