A novel self-aligned double-gate TFT technology

IEEE Electron Device Letters

Volumn 22, Issue 11, 2001, Pages 530-532

  Zhang, Shengdong ^b   Han, Ruqi ^b   Sin, Johnny K O ^a,c   Chan, Mansun ^a,c  

^a IEEE

^b PEKING UNIVERSITY   (China)

^c HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Double gate; Self aligned; Thin film transistor

Indexed keywords

AMORPHOUS SILICON; CHEMICAL MECHANICAL POLISHING; CHEMICAL VAPOR DEPOSITION; CRYSTALLIZATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); GRAIN SIZE AND SHAPE; POLYSILICON; SEMICONDUCTOR DEVICE STRUCTURES; SILICON WAFERS; SUBSTRATES;

DOUBLE-GATE TRANSISTOR; METAL INDUCED UNILATERAL CRYSTALLIZATION; SELF-ALIGNED TRANSISTOR;

THIN FILM TRANSISTORS;

EID: 0035506259     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.962653     Document Type: Article

References (8)

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