Electrical characteristics of new LDD poly-Si TFT structure tolerant to process misalignment

IEEE Electron Device Letters

Volumn 20, Issue 7, 1999, Pages 335-337

  Min, Byung Hyuk ^a   Kanicki, Jerzy ^a  

^a The Department of Civil and Environmental Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHOUS FILMS; AMORPHOUS SILICON; CHEMICAL VAPOR DEPOSITION; CRYSTALLIZATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC PROPERTIES; ELECTRODES; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES;

AMORPHOUS SILICON FILMS; KINK EFFECT; LIGHTLY DOPED DRAIN; MAXIMUM ON-OFF CURRENT RATIO; POLYSILICON THIN FILM TRANSISTOR; PROCESS MISALIGNMENT;

THIN FILM TRANSISTORS;

EID: 0033164973     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.772368     Document Type: Article

References (8)

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