A 100 nm node CMOS technology for system-on-a-chip applications

IEICE Transactions on Electronics

Volumn E85-C, Issue 5, 2002, Pages 1057-1063

  Imai, Kiyotaka ^a   Ono, Atsuki ^a  

^a NEC CORPORATION   (Japan)

Author keywords

CMOS; Gate leakage current; Oxynitride; Threshold voltage

Indexed keywords

CHEMICAL VAPOR DEPOSITION; ELECTRIC FIELD EFFECTS; ION IMPLANTATION; LEAKAGE CURRENTS; LOW TEMPERATURE OPERATIONS; MOSFET DEVICES; NANOTECHNOLOGY; NITRIDING; RAPID THERMAL ANNEALING; SEMICONDUCTING SILICON COMPOUNDS; THICKNESS MEASUREMENT; THRESHOLD VOLTAGE;

DRIVE CURRENT; GATE OXIDE; RADICAL NITRIDATION; RAPID THERMAL HYDROGEN ANNEAL; SHORT CHANNEL EFFECT; STANDBY POWER; SUPPLY VOLTAGE; SYSTEM-ON-A-CHIP;

CMOS INTEGRATED CIRCUITS;

EID: 0036579173     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (12)

1. A 0.13-μm CMOS technology integrating high-speed and low-power/high-density devices with two different well/channel structures
2. CMOS device optomization for system-on-a-chip applications
3. A multi-gate dielectric technology using hydrogen pretreatment for 100 nm generation system-on-a-chip
4. Low-leakage and high-reliability 1.5 nm SiON gate-dielectric using radical oxynitridation for sub-0.1 μm CMOS
5. Radical nitridation in multi-oxide process for 100 nm generation CMOS technology
6. High reliability poly-SiGe/amorphous-Si gate CMOS
7. A 70 nm gate length CMOS technology with 1.0 V operation
8. Effect of wet etched thickness and reoxidation on reliability of dual gate oxide for sub-quarter micron complementary metal-oxide-semiconductor devices
9. Inversion layer mobility under high normal field in nitrided-oxide MOSFETs
10. NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-μm gate CMOS generation