A technology simulation methodology for AC-performance optimization of SiGe HBTs

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 489-492

  Johnson, Jeffrey B ^a   Stricker, Andreas ^a   Joseph, Alvin J ^a   Slinkman, James A ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC; BORON; CALIBRATION; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIFFUSION; EPITAXIAL GROWTH; FREQUENCIES; OPTIMIZATION; PHOSPHORUS; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE;

CUT OFF FREQUENCIES; DEVICE SIMULATION; MAXIMUM OSCILLATION FREQUENCY; TECHNOLOGY SIMULATION;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 0035714370     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced PFET
2. A 0.18μm 90 GHz ft SiGe HBT BiCMOS, ASIC-Compatible, copper interconnect technology for RF and microwave applications
3. A 0.18μm production-ready BiCMOS technology featuring 120/100 GHz (ft/fmax) HBT and ASIC-compatible CMOS using Cu interconnect
4. A 210 GHz silicon germanium bipolar technology for communication systems beyond 40 Gb/s
5. Diffusion in strained Si(Ge)
6. High-frequency characterization of heterojunction bipolar transistors using numerical simulation
7. Prospects of silicon-germanium-based technology for very high-speed circuits