Multi blt dac with corrective gate to drain voltage for optimum matching under gradient temeperature effects

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 1, Issue , 1998, Pages 139-142

  Mojal, Michael ^a  

^a SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; ERROR ANALYSIS; INTEGRATED CIRCUIT LAYOUT; THERMAL EFFECTS; THERMAL GRADIENTS;

FABRICATION ERRORS; GATE-TO-DRAIN VOLTAGE; HIGH POWER; MATCHING ERROR; MULTI-BITS; OPTIMUM DESIGNS; OPTIMUM MATCHING; OPTIMUM VALUE;

DIGITAL TO ANALOG CONVERSION; MOS DEVICES;

CORRECTIVE GATES;

EID: 0032280997     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.1998.813288     Document Type: Conference Paper

References (4)

1. K. Lampar, G. Gielen, W. Sansen, Thermaly Constrained Placement of Analog and Smart Power ICs. P.160, ESSCRIC 96 Proceedings of the 22nd European.
2. A. S. GROVE Physics and Technology of Semiconductors Devices p, 347. John Wiley and Sons, Inc. New York, London, Sydney..
3. W. N. carr and J. P. Mize, MOS/LS1 design and application. N. Y.: McGraw-Hill, 1972, p. 46.
4. R. S. Muller & T. I. Kammins, Device Electronics for Integrated Circuits. N. Y. Wiley 1977