Evolutionary graph generation system with symbolic verification for arithmetic circuit design

Electronics Letters

Volumn 36, Issue 11, 2000, Pages 937-939

  Homma, N ^a   Aoki, T ^a   Higuchi, T ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0001058033     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20000704     Document Type: Article

References (6)

1. AOKI, T., HOMMA, N., and HIGUCHI, T.: 'Evolutionary design of arithmetic circuits', IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 1999, E82-A, (5), pp. 798-806
2. BACK, T., HAMMEL, U., and SCHWEFEL, P.H.: 'Evolutionary computation: Comments on the history and current state', IEEE Trans. Evol. Comput., 1997, 1, (1), pp. 3-13
3. ALLEN, M.B., and ISAACSON, E.L.: 'Numerical analysis for applied science' (John Wiley & Sons, Inc., 1998)
4. KOREN, I.: 'Computer arithmetic algorithms' (Prentice Hall, 1993)
5. DEMPSTER, A.G., and MACLEOD, M.D.: 'Constant integer multiplication using minimum adders', IEE Proc. Circuits Devices Syst., 1994, 141, (5), pp. 407-413
6. HARTLEY, R.I.: 'Subexpression sharing in filters using canonic signed digit multipliers', IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., 1996, 43, (10), pp. 677-688