Impact of component placement in solder joint reliability

Microelectronics Reliability

Volumn 42, Issue 3, 2002, Pages 399-406

  Alander, T ^a   Nurmi, S ^a   Heino, P ^a   Ristolainen, E ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COMPUTATIONAL METHODS; FINITE ELEMENT METHOD; MAGNETOELECTRIC EFFECTS; PRINTED CIRCUIT BOARDS; SOLDERED JOINTS;

BALL GRID ARRAYS (BGA); CHIP SIZE PACKAGES (CSP);

INTEGRATED CIRCUIT LAYOUT;

EID: 0036496807     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(01)00217-7     Document Type: Article

References (14)

1. Solder bump reliability issues on bump layout
2. The roles of DNP (distance to neutral point) on solder joint reliability of area array assemblies
3. Coffin-Manson based fatigue analysis of underfilled DCAs
4. Finite element modeling of thermal fatigue and damage of solder joints in a ceramic ball grid array package
5. Solder joint reliability modeling for a 540-i/o plastic ball-grid-array assembly
6. Solder joint fatigue life model
7. An internal variable constitutive model for hot working of metals
8. The necessity of reexamining previous life prediction analyses of solder joints in electronic packages
9. Time-dependent material modeling for finite element analyses of flip chips
10. Effect of simulation methodology on solder joint crack growth studies
11. Measurement of solder bump lifetime as a function of underfill material properties