Solder bump reliability—issues on bump layout

IEEE Transactions on Advanced Packaging

Volumn 23, Issue 4, 2000, Pages 715-720

  Alander, Tapani ^a   Heino, Pekka ^a   Ristolainen, Eero ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; FLIP CHIP DEVICES; HEAT TRANSFER; INTEGRATED CIRCUIT LAYOUT; PRINTED CIRCUIT BOARDS; RELIABILITY; THREE DIMENSIONAL; VISCOPLASTICITY;

BOARD SIZE; BUMP LAYOUT; FLIP CHIP PACKAGE; SOLDER BUMP; VISCOPLASTIC MATERIAL;

SOLDERING;

EID: 0034318152     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/6040.883763     Document Type: Article

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