Performance driven global routing through gradual refinement

VLSI Design

Volumn 15, Issue 3, 2002, Pages 595-604

  Hu, Jiang ^a   Sapatnekar, Sachin S ^b  

^a TEXAS A AND M UNIVERSITY   (United States)

^b University of Minnesota   (United States)

Author keywords

Deep submicron; Glo bal routing; Interconnect; Physical design; Timing optimization; VLSI

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CONSTRAINT THEORY; HEURISTIC METHODS; INTERCONNECTION NETWORKS; LINEAR PROGRAMMING; RANDOM PROCESSES; VLSI CIRCUITS;

DEEP SUBMICRON; GLOBAL ROUTING; GRADUAL REFINEMENT; PHYSICAL DESIGN; TIMING OPTIMIZATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036458524     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1080/1065514021000012219     Document Type: Article

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