Performance-driven interconnect global routing

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1996, Pages 132-136

  Wang, D ^a   Kuh, E S ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; ITERATIVE METHODS; OPTIMIZATION; PRINTED CIRCUIT DESIGN;

GLOBAL ROUTING;

VLSI CIRCUITS;

EID: 0029715886     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)