Overcoming wireload model uncertainty during physical design

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2001, Pages 182-189

  Gopalakrishnan, P ^a   Odabasioglu, A ^a   Pileggi, L ^a   Raje, S ^a  

^a Monterey Design Systems   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; ELECTRIC LOADS; HIERARCHICAL SYSTEMS; PRODUCT DESIGN;

WIRELOAD MODELS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034825531     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/369691.369769     Document Type: Conference Paper

References (13)

1. An integrated placement and synthesis approach for timing closure of PowerPC microprocessors
2. Getting to the bottom of deep submicron
3. DSM: It's the heights and not the depths that are dangerous
4. Placement and average interconnection lengths of computer logic
5. On wirelength estimations for row-based placement
6. A wire length estimation technique utilizing neighborhood density equations
7. Accurate interconnection length estimations for predictions early in the design cycle
8. Interconnection length estimation for optimized standard cell layouts
9. Average interconnection length estimation for random and optimized placements
10. Pre-layout estimation of individual wire lengths