Multi-level logic optimization for low power using local logic transformations

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1996, Pages 270-277

  Wang, Qi ^a   Vrudhula, Sarma B K ^a  

^a UNIVERSITY OF ARIZONA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMBINATORIAL SWITCHING; DELAY CIRCUITS; FORMAL LOGIC; LOGIC DESIGN; MATHEMATICAL MODELS; OPTIMIZATION; POWER SUPPLY CIRCUITS; REDUNDANCY; SWITCHING CIRCUITS;

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR COMBINATIONAL LOGIC NETWORK; LOCAL LOGIC TRANSFORMATIONS;

COMBINATORIAL CIRCUITS;

EID: 0030406539     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)