A wide-range and fixed latency of one clock cycle delay-locked loop

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2002, Pages

  Chang, Hsiang Hui ^a   Lin, Jyh Woei ^a   Liu, Shen Iuan ^a  

^a Taipei County Hospital and Taiwan Medical University   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC DELAY LINES; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; HARMONIC ANALYSIS; INTEGRATED CIRCUIT MANUFACTURE; JITTER; TIMING CIRCUITS;

DELAY LOCKED LOOP; HARMONIC LOCKING PROBLEM; PHASE SELECTION CIRCUIT; START CONTROLLED CIRCUIT;

CMOS INTEGRATED CIRCUITS;

EID: 0036290989     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Monolithic phase-locked loops and clock recovery circuits: Theory and design
2. Multiple target clock distribution with arbitrary delay interconnects
3. Clock buffer chip with multiple target automatic skew compensation
4. An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance
5. A 64-Mbit, 640-Mbyte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-Mbyte memory system
6. CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator
7. A 256-Mb double-data-rate SDRAM with a 10-mW analog DLL circuit
8. A 66-400 MHz, adaptive-lock-mode DLL circuit duty-cycle error correction
9. A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL
10. Low-jitter process-independent DLL and PLL based on self-biased techniques