Multiple target clock distribution with arbitrary delay interconnects

Electronics Letters

Volumn 34, Issue 22, 1998, Pages 2119-2120

  Aguiar, R L ^a   Santos, D M ^a  

^a UNIVERSITY OF AVEIRO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC DELAY LINES; MULTICHIP MODULES; SYNCHRONIZATION;

DELAY LOCKED LOOP; MULTIPLE TARGET CLOCK DISTRIBUTION; VOLTAGE CONTROLLED DELAY LINES;

TIMING CIRCUITS;

EID: 0032181132     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19981520     Document Type: Article

References (5)

1. GEANNOPOULOS, G., and DAI, X.: 'An adaptive digital deskewing circuit for clock distribution networks'. IEEE Int. Solid-State Conf. ISSCC'98, February 1998, pp. 400-401
2. SHIBAYAMA, A., et al.: 'Device deviation tolerant over-1GHz clock distribution scheme with skew-immune race-free impulse latch circuits'. IEEE Int. Solid-State Conf. ISSCC'98, February 1998, pp. 402-403
3. SUTOH, H., and YAMAKOSHI, K.: 'A clock distribution technique with an automatic skew compensation circuit', IEICE Trans. Electron., 1998, E81-C, (2), pp. 277-283
4. AGUIAR, R.L., and SANTOS, D.M.: 'Wide-area clock distribution using controlled delay lines'. 5th IEEE Int. Conf. Electronics, Circuits and Systems, ICECS'98, Lisbon, September 1998
5. SVENSSON, C., and AFGHAHI, M.: 'On RC line delays and scaling in VLSI systems', Electron. Lett., 1988, 24, (9), pp. 562-563