Data path placement with regularity

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 264-270

  Ye, Terry Tao ^a   De Micheli, Giovanni ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; COMPUTER AIDED DESIGN; DATA FLOW ANALYSIS; DATA HANDLING; DESIGN; FLOW GRAPHS; GRAPHIC METHODS; HEURISTIC ALGORITHMS; ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; HEURISTIC METHODS; HIGH LEVEL LANGUAGES; INTERCONNECTION NETWORKS; VLSI CIRCUITS;

DATA PROCESSING FUNCTIONS; LINEAR PLACEMENT; PERFORMANCE REQUIREMENTS; PHYSICAL DESIGN; PHYSICAL MODEL; SYSTEMS ON CHIPS; VLSI DESIGN; WIRE LENGTH;

DATA FLOW GRAPHS; INTEGRATED CIRCUIT LAYOUT;

ABSTRACT PHYSICAL MODEL; DATA FLOW GRAPH; DATA PATH PLACEMENT; HEURISTIC ALGORITHM; SYSTEMS-ON-CHIP;

EID: 0034474911     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896484     Document Type: Conference Paper

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