High density datapath layout generation method under path delay constraints

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1993, Pages

  Nakao, ^a   Kitada, ^a   Hayashikoshi, Michiko ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN;

ARRAY-COMPILER; HIGH DENSITY DATAPATH LAYOUT GENERATION; PATH DELAY CONSTRAINTS;

PARALLEL PROCESSING SYSTEMS;

EID: 0027290253     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)