Design of low-error fixed-width multiplier for DSP applications

Electronics Letters

Volumn 33, Issue 19, 1997, Pages 1597-1598

  Jou, Jer Min ^a   Kuang, Shiann Rong ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

Digital signal processing; Multiplying circuits

Indexed keywords

DIGITAL SIGNAL PROCESSING; ERROR ANALYSIS; LOGIC GATES;

FIXED WIDTH PARALLEL MULTIPLIERS;

MULTIPLYING CIRCUITS;

EID: 0031234076     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19971087     Document Type: Article

References (4)

1. JOU, J.M., KUANG, S.R., CHEN, V.L., and CHIANG, C.Y.: 'An on line adaptive data compression chip using arithmetic codes'. ISCAS, 1996, Vol. IV, pp. 360-363
2. TERRELL, T.J.: 'Introduction to digital filters' (Halsted Press, John Wiley & Sons Inc., NY, 1988)
3. KIDAMBI, S.S., EL-GUIBALY, F., and ANTONIOU, A.: 'Area-efficient multipliers for digital signal processing applications', IEEE Trans. Circuits Syst. II. 1996, 43, (2), pp. 90-94
4. 0.8μM SPDM Technology Manual, Computer & Communication Laboratory, Industry Technology Research Institute, Republic of China