Spacer FinFET: Nano-scale CMOS technology for the terabit era

2001 International Semiconductor Device Research Symposium, ISDRS 2001 - Proceedings

Volumn , Issue , 2001, Pages 543-546

  Choi, Yang Kyu ^a   King, Tsu Jae ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; MOSFET DEVICES; NANOTECHNOLOGY; PHOTOLITHOGRAPHY; SEMICONDUCTOR DEVICES;

CRITICAL DIMENSION; DOUBLE-GATE MOSFETS; E-BEAM LITHOGRAPHY; FIN STRUCTURES; NANO-SCALE CMOS; SACRIFICIAL LAYER; SPACER LAYER; SPACER LITHOGRAPHY;

LITHOGRAPHY;

EID: 84961789577     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISDRS.2001.984573     Document Type: Conference Paper

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