Electrostatic discharge induced oxide breakdown characterization in a 0.1 μm CMOS technology

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2002, Pages 170-174

  Salman, Akram ^a   Gauthier, Robert ^a   Wu, Ernest ^a   Riess, Philipp ^a   Putnam, Chris ^a   Muhammad, Mujahid ^a   Woo, Min ^a   Ioannou, Dimitris ^a  

^a GEORGE MASON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEGRADATION; ELECTRIC BREAKDOWN; ELECTROSTATICS; LEAKAGE CURRENTS; SEMICONDUCTING SILICON;

ELECTROSTATIC DISCHARGE (ESD); SOURCE CONTACT-TO-GATE SPACING (SCG); TRANSMISSION LINE PULSE (TLP);

CMOS INTEGRATED CIRCUITS;

EID: 0036085795     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. Evaluation of f/diode-based and NMOS/Lnpn-based ESD protection strategies in a triple gate oxide thickness 0.13 μm CMOS logic technology
2. Hot carrier degradation and ESD in submicrometer CMOS technologies: How do they interact?
3. Characterization and investigation of the interaction between hot electron and electrostatic discharge stressesusing NMOS devices in 0.13μm CMOS technology
4. Analysis of snapback behavior on the ESD capability of sub 0.2 μm NMOS
5. High performance 50 nm CMOS devices for microprocessor and embedded processor core applications
6. Breakdown and latent damage of ultra-thin oxides under ESD stress conditions
7. Mechanisms for stress-induced leakage currents in silicon dioxide films