-
1
-
-
0009667182
-
Temperature dependence of avalanche multiplication in semiconductors
-
C. Crowell and S. M. Sze, "Temperature dependence of avalanche multiplication in semiconductors," Appl. Phys. Lett., vol. 9, p. 242, 1966.
-
(1966)
Appl. Phys. Lett.
, vol.9
, pp. 242
-
-
Crowell, C.1
Sze, S.M.2
-
2
-
-
33747904204
-
-
C. A. Eee, R. A. Eogan, R. E. Batdorf, J. J. Kleinmack, and W. Wiegmann, Phys. Rev., vol. 134, p. A761, 1964.
-
(1964)
Phys. Rev.
, vol.134
-
-
Eee, C.A.1
Eogan, R.A.2
Batdorf, R.E.3
Kleinmack, J.J.4
Wiegmann, W.5
-
5
-
-
0006219880
-
The mechanisms of hot carrier degradation
-
C. T. Wang, Ed. New York: Van Nostrand-Reinhold, ch. 1.
-
P. Heremans, R. Bellens, G. Groeseneken, A. V. Schwerin, W. Weber, M. Brox, and H. E. Maes, "The mechanisms of hot carrier degradation," in Hot Carrier Design Considerations for MOS Devices and Circuits, C. T. Wang, Ed. New York: Van Nostrand-Reinhold, 1992, ch. 1.
-
(1992)
Hot Carrier Design Considerations for MOS Devices and Circuits
-
-
Heremans, P.1
Bellens, R.2
Groeseneken, G.3
Schwerin, A.V.4
Weber, W.5
Brox, M.6
Maes, H.E.7
-
7
-
-
0029373408
-
Hot carrier degradation in submicrometre MOSFET's: From uniform injection towards the real operating conditions
-
G. Groeseneken, R. Bellens, G. Van den Bosch, and H. E. Maes, "Hot carrier degradation in submicrometre MOSFET's: From uniform injection towards the real operating conditions," Semicond. Sei. Technol., vol. 10, pp. 1208-1220, 1995.
-
(1995)
Semicond. Sei. Technol.
, vol.10
, pp. 1208-1220
-
-
Groeseneken, G.1
Bellens, R.2
Van Den Bosch, G.3
Maes, H.E.4
-
8
-
-
0024124856
-
Consistent model for the hot carrier degradation in n-channel and p-channel MOSFET's
-
P. Heremans, R. Bellens, G. Groeseneken, and H. E. Maes, "Consistent model for the hot carrier degradation in n-channel and p-channel MOSFET's," IEEE Trans. Electron Devices, vol. 35, p. 2194, 1988.
-
(1988)
IEEE Trans. Electron Devices
, vol.35
, pp. 2194
-
-
Heremans, P.1
Bellens, R.2
Groeseneken, G.3
Maes, H.E.4
-
9
-
-
0027542095
-
Time dependence of p-MOSFET hot-carrier degradation measured and interpreted consistently over ten orders of magnitude
-
R. Woltjer, A. Hamada, and E. Takeda, "Time dependence of p-MOSFET hot-carrier degradation measured and interpreted consistently over ten orders of magnitude," IEEE Trans. Electron Devices, vol. 40, p. 392, 1993.
-
(1993)
IEEE Trans. Electron Devices
, vol.40
, pp. 392
-
-
Woltjer, R.1
Hamada, A.2
Takeda, E.3
-
10
-
-
0025419847
-
Temperature dependence of channel hot carrier degradation in n-channel MOSFET's
-
P. Heremans, G. Van den Bosch, R. Bellens, G. Groeseneken, and H. E. Maes, "Temperature dependence of channel hot carrier degradation in n-channel MOSFET's," IEEE Trans. Electron Devices, vol. 37, p. 980, 1990.
-
(1990)
IEEE Trans. Electron Devices
, vol.37
, pp. 980
-
-
Heremans, P.1
Van Den Bosch, G.2
Bellens, R.3
Groeseneken, G.4
Maes, H.E.5
-
11
-
-
84945713471
-
Hot-electron-induced MOSFET degradation-model, monitor, and improvement
-
C. Hu, S. C. Tarn, F. C. Hsu, P. K. Ko, and K. W. Terrill, "Hot-electron-induced MOSFET degradation-model, monitor, and improvement," IEEE Trans. Electron Devices, vol. ED-32, p. 375, 1985.
-
(1985)
IEEE Trans. Electron Devices
, vol.ED-32
, pp. 375
-
-
Hu, C.1
Tarn, S.C.2
Hsu, F.C.3
Ko, P.K.4
Terrill, K.W.5
-
12
-
-
0020733451
-
An empirical model for device degradation due to hot-carrier injection (MOSFETs)
-
E. Takeda and N. Suzuki, "An empirical model for device degradation due to hot-carrier injection (MOSFETs)," IEEE Electron Device Lett., vol. EDE-4, p.3, 1983.
-
(1983)
IEEE Electron Device Lett.
, vol.EDE-4
, pp. 3
-
-
Takeda, E.1
Suzuki, N.2
-
13
-
-
0021201529
-
A reliable approach to charge pumping measurements in MOS transistors
-
G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, "A reliable approach to charge pumping measurements in MOS transistors," IEEE Trans. Electron Devices, vol. ED-31, p. 42, 1984.
-
(1984)
IEEE Trans. Electron Devices
, vol.ED-31
, pp. 42
-
-
Groeseneken, G.1
Maes, H.E.2
Beltran, N.3
De Keersmaecker, R.F.4
-
14
-
-
0024705114
-
Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation
-
P. Heremans, J. Witters, G. Groeseneken, and H. E. Maes, "Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation," IEEE Trans. Electron Devices, vol. 36, p. 1318, 1989.
-
(1989)
IEEE Trans. Electron Devices
, vol.36
, pp. 1318
-
-
Heremans, P.1
Witters, J.2
Groeseneken, G.3
Maes, H.E.4
-
15
-
-
0022957159
-
A novel submicron LDD transistor with inverse-T gate structure
-
T. Huang, W. W. Yao, R. A. Martin, A. G. Lewis, M. Koyanagi, and J. Y. Chen, "A novel submicron LDD transistor with inverse-T gate structure," IEDM Tech. Dig., p. 742, 1986.
-
(1986)
IEDM Tech. Dig.
, pp. 742
-
-
Huang, T.1
Yao, W.W.2
Martin, R.A.3
Lewis, A.G.4
Koyanagi, M.5
Chen, J.Y.6
-
16
-
-
0024124289
-
Impact of the gate-drain overlapped device (GOLD) for deep submicrometer VLSI
-
R. Izawa, T. Kure, and E. Takeda, "Impact of the gate-drain overlapped device (GOLD) for deep submicrometer VLSI," IEEE Trans. Electron Devices, vol. 35, p. 2088, 1988.
-
(1988)
IEEE Trans. Electron Devices
, vol.35
, pp. 2088
-
-
Izawa, R.1
Kure, T.2
Takeda, E.3
-
17
-
-
0030241404
-
Performance and reliability aspects of FOND: A new deep submicron CMOS device concept
-
R. Bellens, G. Van den Bosch, P. Habas, J. P. Mieville, G. Badenes, A. Clerix, G. Groeseneken, L. Deferm, and H. Maes, "Performance and reliability aspects of FOND: A new deep submicron CMOS device concept," IEEE Trans. Electron Devices, vol. 43, p. 1407, 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.43
, pp. 1407
-
-
Bellens, R.1
Van Den Bosch, G.2
Habas, P.3
Mieville, J.P.4
Badenes, G.5
Clerix, A.6
Groeseneken, G.7
Deferm, L.8
Maes, H.9
-
18
-
-
0026938421
-
Deep-submicrometer largeangle-tilt implanted drain (LATID) technology
-
T. Hori, J. Hirase, Y Odake, and T. Yasui, "Deep-submicrometer largeangle-tilt implanted drain (LATID) technology," IEEE Trans. Electron Devices, vol. 39, p. 2312, 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, pp. 2312
-
-
Hori, T.1
Hirase, J.2
Odake, Y.3
Yasui, T.4
-
19
-
-
85034123855
-
Silicon oxynitride gate dielectrics for scaled CMOS
-
C. G. Sodini and K. S. Krisch, "Silicon oxynitride gate dielectrics for scaled CMOS," IEDM Tech. Dig., p. 617, 1992.
-
(1992)
IEDM Tech. Dig.
, pp. 617
-
-
Sodini, C.G.1
Krisch, K.S.2
-
20
-
-
0027642871
-
Nitrided gate-oxide CMOS technology for improved hot-carrier reliability
-
T. Hori, "Nitrided gate-oxide CMOS technology for improved hot-carrier reliability," Proc. Insulating Films on Semiconductors (INFOS), Microelectronic Engineering, vol. 22, p. 245, 1993.
-
(1993)
Proc. Insulating Films on Semiconductors (INFOS), Microelectronic Engineering
, vol.22
, pp. 245
-
-
Hori, T.1
-
21
-
-
0026938075
-
Hot-carrier-induced degradation of gate dielectrics grown in nitrous oxide under accelerated aging
-
A. Ditali, V Mathews, and P. Fazan, "Hot-carrier-induced degradation of gate dielectrics grown in nitrous oxide under accelerated aging," IEEE Electron Device Lett., vol. 13, p. 538, 1992.
-
(1992)
IEEE Electron Device Lett.
, vol.13
, pp. 538
-
-
Ditali, A.1
Mathews, V.2
Fazan, P.3
-
22
-
-
0028416619
-
Electrical characteristics of rapid thermal nitrided-oxide gate n- And p-MOSFET's with less than 1 atom% nitrogen concentration
-
H. S. Momose, T. Morimoto, Y Ozawa, K. Yamabe, and H. Iwai, "Electrical characteristics of rapid thermal nitrided-oxide gate n- and p-MOSFET's with less than 1 atom% nitrogen concentration," IEEE Trans. Electron Devices, vol. 41, p. 546, 1994.
-
(1994)
IEEE Trans. Electron Devices
, vol.41
, pp. 546
-
-
Momose, H.S.1
Morimoto, T.2
Ozawa, Y.3
Yamabe, K.4
Iwai, H.5
-
23
-
-
0030126232
-
Reduction of hot electron degradation in metal oxide semiconductor transistors by deuterium processing
-
J. W. Lyding, K. Hess, and I. C. Kizilyalli, "Reduction of hot electron degradation in metal oxide semiconductor transistors by deuterium processing," Appl. Phys. Lett., vol. 68 p. 25-26, 1996.
-
(1996)
Appl. Phys. Lett.
, vol.68
, pp. 25-26
-
-
Lyding, J.W.1
Hess, K.2
Kizilyalli, I.C.3
-
24
-
-
0033887302
-
On the mechanism for interface trap generation in MOS transistors due to channel hot carrier stressing
-
Z. Chen, K. Hess, J. Lee, J. W. Lyding, E. Rosenbaum, I. Kizilyalli, S. Chetlur, and R. Huang, "On the mechanism for interface trap generation in MOS transistors due to channel hot carrier stressing," IEEE Electron Device Lett., vol. 21, p. 24, 2000.
-
(2000)
IEEE Electron Device Lett.
, vol.21
, pp. 24
-
-
Chen, Z.1
Hess, K.2
Lee, J.3
Lyding, J.W.4
Rosenbaum, E.5
Kizilyalli, I.6
Chetlur, S.7
Huang, R.8
-
25
-
-
0021300334
-
Snapback induced gate dielectric breakdown in graded junction MOS structures
-
S. Shabde, G. Simmons, A. Baluni, and R. Back, "Snapback induced gate dielectric breakdown in graded junction MOS structures," in Proc. IRPS, 1984, p. 165.
-
(1984)
Proc. IRPS
, pp. 165
-
-
Shabde, S.1
Simmons, G.2
Baluni, A.3
Back, R.4
-
26
-
-
0022563531
-
ESD protection reliability in 1 //mCMOS technologies
-
C. Duvvury, R. A. McPhee, D. A. Baglee, and R. N. Rountree, "ESD protection reliability in 1 //mCMOS technologies,"in Proc. IRPS, 1986, p. 199.
-
(1986)
Proc. IRPS
, pp. 199
-
-
Duvvury, C.1
McPhee, R.A.2
Baglee, D.A.3
Rountree, R.N.4
-
27
-
-
0024124558
-
The effects of interconnect process and snapback voltage on the ESD failure threshold of nMOS transistors
-
K. L. Chen, "The effects of interconnect process and snapback voltage on the ESD failure threshold of nMOS transistors," Trans. Electron Devices, vol. 35, p. 2140, 1988.
-
(1988)
Trans. Electron Devices
, vol.35
, pp. 2140
-
-
Chen, K.L.1
-
28
-
-
0024861842
-
ESD phenomena in graded junction devices
-
C. Duvvury, R. Rountree, H. J. Stiegler, T. Polgreen, and D. Corum, "ESD phenomena in graded junction devices," in Proc. IRPS, 1989, p. 71.
-
(1989)
Proc. IRPS
, pp. 71
-
-
Duvvury, C.1
Rountree, R.2
Stiegler, H.J.3
Polgreen, T.4
Corum, D.5
-
29
-
-
0025577026
-
Reliability design of p±-pocket implant LDD transistors
-
C. Duvvury, T. C. Holloway, D. Paradis, and A. K. Duong, "Reliability design of p±-pocket implant LDD transistors," IEDM Tech. Dig., p. 215, 1990.
-
(1990)
IEDM Tech. Dig.
, pp. 215
-
-
Duvvury, C.1
Holloway, T.C.2
Paradis, D.3
Duong, A.K.4
-
30
-
-
0011159445
-
Process and design optimization for advanced CMOS I/O ESD protection
-
S. Daniel and G. Krieger, "Process and design optimization for advanced CMOS I/O ESD protection," in Proc. EOS/ESD Symp., 1990, p. 206.
-
(1990)
Proc. EOS/ESD Symp.
, pp. 206
-
-
Daniel, S.1
Krieger, G.2
-
31
-
-
0042816429
-
ESD improvement using low concentrations of arsenic implantation in CMOS output buffers
-
M. D. Chaîne, S. M. Desai, C. F. Dunn, D. Dolby, W. B. Holland, and T. Pekny, "ESD improvement using low concentrations of arsenic implantation in CMOS output buffers," in Proc. EOS/ESD Symp., 1992, p. 136.
-
(1992)
Proc. EOS/ESD Symp.
, pp. 136
-
-
Chaîne, M.D.1
Desai, S.M.2
Dunn, C.F.3
Dolby, D.4
Holland, W.B.5
Pekny, T.6
-
32
-
-
0042315267
-
MOSFET drain engineering for ESD performance
-
Y Wei, Y Loh, C. Wang, and C. Hu, "MOSFET drain engineering for ESD performance," in Proc. EOS/ESD Symp., 1992, p. 143.
-
(1992)
Proc. EOS/ESD Symp.
, pp. 143
-
-
Wei, Y.1
Loh, Y.2
Wang, C.3
Hu, C.4
-
33
-
-
0030165949
-
Building-in ESD/EOS reliability for sub-halfmicron CMOS processes
-
C. H. Diaz, T. E. Kopley, and P. J. Marcoux, "Building-in ESD/EOS reliability for sub-halfmicron CMOS processes," IEEE Trans. Electron Devices, vol. 43, p. 991, 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.43
, pp. 991
-
-
Diaz, C.H.1
Kopley, T.E.2
Marcoux, P.J.3
-
34
-
-
0004138929
-
-
Ph.D Thesis, Technical Univ., Shaker Verlag, Munich
-
C. RUSS, "ESD protection devices for CMOS technologies: Processing impact, modeling and testing issues," Ph.D Thesis, Technical Univ., Shaker Verlag, Munich, 1999.
-
(1999)
ESD Protection Devices for CMOS Technologies: Processing Impact, Modeling and Testing Issues
-
-
Russ, C.1
-
35
-
-
0038367182
-
Building in reliability with latch-up, ESD and hot carrier effects on a 0.25 μm CMOS technology
-
C. Leroux, P. Salome, G. Reimbold, D. Blachier, G. Guegan, and M. Bonis, "Building in reliability with latch-up, ESD and hot carrier effects on a 0.25 μm CMOS technology," Microelectron. Reliab., vol. 38, p. 1547, 1998.
-
(1998)
Microelectron. Reliab.
, vol.38
, pp. 1547
-
-
Leroux, C.1
Salome, P.2
Reimbold, G.3
Blachier, D.4
Guegan, G.5
Bonis, M.6
-
36
-
-
0023829359
-
Hot-electron reliability and ESD latent damage
-
S. Aur, A. Chatterjee, and T. Polgreen, "Hot-electron reliability and ESD latent damage," in Proc. IRPS, 1988, p. 15.
-
(1988)
Proc. IRPS
, pp. 15
-
-
Aur, S.1
Chatterjee, A.2
Polgreen, T.3
-
37
-
-
0024123504
-
Hot-electron reliability and ESD latent damage
-
_, "Hot-electron reliability and ESD latent damage," IEEE Trans. Electron Devices, vol. 35, p. 2189, 1988.
-
(1988)
IEEE Trans. Electron Devices
, vol.35
, pp. 2189
-
-
-
38
-
-
0025503641
-
Impact of snapback-induced hole inuection on gate oxide reliability of N-MOSFETs
-
K. R. Mistry, D. Krakauer, and B. S. Doyle, "Impact of snapback-induced hole inuection on gate oxide reliability of N-MOSFETs," IEEE Electron Device Lett., vol. 11, p. 460, 1990.
-
(1990)
IEEE Electron Device Lett.
, vol.11
, pp. 460
-
-
Mistry, K.R.1
Krakauer, D.2
Doyle, B.S.3
-
39
-
-
0024124290
-
The effect of channel hot-carrier stressing on gate-oxide integrity in MOSFETs
-
I. C. Chen, J. Y. Choi, T. Y. Chan, and C. Hu, "The effect of channel hot-carrier stressing on gate-oxide integrity in MOSFETs," IEEE Trans. Electron Devices, vol. 35, p. 2253, 1988.
-
(1988)
IEEE Trans. Electron Devices
, vol.35
, pp. 2253
-
-
Chen, I.C.1
Choi, J.Y.2
Chan, T.Y.3
Hu, C.4
-
40
-
-
0026136650
-
Reoxidized nitrided oxides (RNO) for latent ESD-resistant MOSFET dielectrics
-
B. S. Doyle and K. R. Mistry, "Reoxidized nitrided oxides (RNO) for latent ESD-resistant MOSFET dielectrics," IEEE Electron Device Lett., vol. 12, p. 184, 1991.
-
(1991)
IEEE Electron Device Lett.
, vol.12
, pp. 184
-
-
Doyle, B.S.1
Mistry, K.R.2
-
41
-
-
0031653444
-
A study of ESD-induced latent damage in CMOS integrated circuits
-
Y Huh, M. G. Lee, J. Lee, H. C. Jung, T. Li, D. H. Song, Y. J. Lee, J. M. Hwang, Y. K. Sung, and S. M. Kang, "A study of ESD-induced latent damage in CMOS integrated circuits," in Proc. IRPS, 1998, p. 279.
-
(1998)
Proc. IRPS
, pp. 279
-
-
Huh, Y.1
Lee, M.G.2
Lee, J.3
Jung, H.C.4
Li, T.5
Song, D.H.6
Lee, Y.J.7
Hwang, J.M.8
Sung, Y.K.9
Kang, S.M.10
-
42
-
-
0032308764
-
ESD-related process effects in mixed-voltage sub-0.5 μm technologies
-
V. Gupta, A. Amerasekera, S. Ramaswamy, and A. Tsao, "ESD-related process effects in mixed-voltage sub-0.5 μm technologies," in Proc. EOS/ESD Symp., 1998, p. 161.
-
Proc. EOS/ESD Symp., 1998
, pp. 161
-
-
Gupta, V.1
Amerasekera, A.2
Ramaswamy, S.3
Tsao, A.4
-
43
-
-
0032316866
-
ESD protection for mixed-voltage I/O using nMOS transistors stacked in a cascode configuration
-
W. R. Anderson and D. B. Krakauer, "ESD protection for mixed-voltage I/O using nMOS transistors stacked in a cascode configuration," in Proc. EOS/ESD Symp., 1998, p. 54.
-
(1998)
Proc. EOS/ESD Symp.
, pp. 54
-
-
Anderson, W.R.1
Krakauer, D.B.2
-
44
-
-
0026820351
-
Improving the ESD failure threshold of silicided nMOS output transistors by ensuring uniform current flow
-
T. Polgreen and A. Chatterjee, "Improving the ESD failure threshold of silicided nMOS output transistors by ensuring uniform current flow," IEEE Trans. Electron Devices, vol. 39, pp. 379-388, 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, pp. 379-388
-
-
Polgreen, T.1
Chatterjee, A.2
-
45
-
-
0026838967
-
Dynamic gate coupling of nMOS for efficient output ESD protection
-
C. Duvvury and C. Diaz, "Dynamic gate coupling of nMOS for efficient output ESD protection," in Proc. IRPS, 1992, p. 141.
-
(1992)
Proc. IRPS
, pp. 141
-
-
Duvvury, C.1
Diaz, C.2
-
46
-
-
33747060861
-
Achieving uniform nMOS device power distribution for sub-micron ESD reliability
-
C. Duvvury, C. Diaz, and T. Haddock, "Achieving uniform nMOS device power distribution for sub-micron ESD reliability," IEDM Tech. Dig., p. 131, 1992.
-
(1992)
IEDM Tech. Dig.
, pp. 131
-
-
Duvvury, C.1
Diaz, C.2
Haddock, T.3
-
47
-
-
0029490088
-
A hot-carrier triggered SCR for smart power bus ESD protection
-
J. T. Watt and A. J. Walker, "A hot-carrier triggered SCR for smart power bus ESD protection," IEDM Tech. Dig., p. 341, 1995.
-
(1995)
IEDM Tech. Dig.
, pp. 341
-
-
Watt, J.T.1
Walker, A.J.2
|