Software synthesis from synchronous specifications using logic simulation techniques

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 319-324

  Jiang, Yunjian ^a   Brayton, Robert K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SOFTWARE; MATHEMATICAL MODELS; OPTIMIZATION;

SOFTWARE SYNTHESIS;

EMBEDDED SYSTEMS;

EID: 0036059571     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/514001.514002     Document Type: Conference Paper

References (24)

1. Fast functional simulation using branching program
2. Synthesis of software programs for embedded control applications
3. Hw/sw partitioning and code generation of embedded control applications on a reconfigurable architecture platform
4. Esterel on hardware
5. The Esterel synchronous programming language: Design, semantics, implementation
6. Automatic functional test ganeration using the extended finite state machine model
7. Compiling esterel into sequential code
8. Semi-algebraic methods for multi-valued logic
9. Cronos: A separate compilation toolset for modular esterel applications
10. Don't cares and multi-valued logic network minimization
11. Logic optimization and code generation for embedded control applications
12. Free MDD-based software optimization techniques for embedded systems
13. Event driven simulation without loops or conditionals
14. Fast discrete function evaluation using decision diagrams
15. SIS: A system for sequential circuit synthesis
16. Latch optimization in circuits ganerated from high-level descriptions
17. Synthesis of embedded software using free-choice petri nets
18. Back-tracing and event-driven techniques in high-level simulation with decision diagrams
19. Efficient compilation of Esterel for real-time embedded systems