Latch optimization in circuits generated from high-level descriptions

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1996, Pages 428-435

  Sentovich, Ellen M ^a   Toma, Horia ^a   Berry, Gerard ^a  

^a PSL RESEARCH UNIVERSITY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; FINITE AUTOMATA; FLIP FLOP CIRCUITS; HIGH LEVEL LANGUAGES; OPTIMIZATION; STATE ASSIGNMENT;

FINITE STATE MACHINE (FSM); LATCH/LOGIC TRADEOFFS; NEXT STATE FUNCTIONS; OUTPUT FUNCTIONS;

LOGIC CIRCUITS;

EID: 0030389242     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)