On synthesis-for-testability of combinational logic circuits

Proceedings - Design Automation Conference

Volumn , Issue , 1995, Pages 126-132

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DELAY CIRCUITS; ELECTRIC FAULT CURRENTS; ELECTRIC NETWORK SYNTHESIS; LOGIC GATES; MATHEMATICAL MODELS; NUMERICAL METHODS; RANDOM PROCESSES;

COMBINATIONAL LOGIC CIRCUITS; COMPARISON FUNCTIONS; PATH DELAY FAULTS; RANDOM PATTERN TESTABILITY; STUCK AT FAULTS;

COMBINATORIAL CIRCUITS;

EID: 0029229314     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/217474.217518     Document Type: Conference Paper

References (17)