Are wires plannable?

2001 International Workshop on System-Level Interconnect Prediction (SLIP 2001)

Volumn , Issue , 2001, Pages 59-66

  Otten, Ralph H J M ^a   Garcea, Giuseppe S ^b  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; ELECTRIC WIRE; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS;

GLOBAL WIRE DELAYS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035788948     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368640.368707     Document Type: Conference Paper

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