Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities

IEEE Transactions on Instrumentation and Measurement

Volumn 50, Issue 6, 2001, Pages 1725-1747

  Das, Sunil R ^a,b,c   Ramamoorthy, C V ^a,b   Assaf, Mansour H ^c   Petriu, Emil M ^a,c   Jone, Wen Ben ^a,d  

^a IEEE   (Canada)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF OTTAWA   (Canada)

^d 705 Engineering Research Center   (United States)

Author keywords

Built in self test (BIST); Circuit under test (CUT); Derived sequences; Detectable error probability estimates; Hamming distance; Optimal sequence mergeability; Parity tree space compactors; Sequence weights; Space compaction; Time compaction

Indexed keywords

BUILT-IN SELF TESTING; CIRCUIT UNDER TEST; COMBINATIONAL BENCHMARK CIRCUITS; FAILURE PROBABILITIES; SPACE COMPARATOR;

ALGORITHMS; COMPUTER HARDWARE; COMPUTER SIMULATION; DATA COMPRESSION; ERROR ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; PROBABILITY; SYSTEMS ANALYSIS;

INTEGRATED CIRCUIT TESTING;

EID: 0035719333     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/19.982974     Document Type: Article

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