A novel approach to designing aliasing-free space compactors based on switching theory formulation

Conference Record - IEEE Instrumentation and Measurement Technology Conference

Volumn 1, Issue , 2001, Pages 198-203

  Das, S R ^a   Assaf, M H ^a   Petriu, E M ^a   Jone, W B ^a   Chakrabarty, K ^a  

^a NONE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; DIGITAL INTEGRATED CIRCUITS; ERRORS; LOGIC GATES; PROBABILITY; RANDOM PROCESSES;

CIRCUIT UNDER TEST; ZERO-ALIASING SPACE COMPACTORS;

INTEGRATED CIRCUIT TESTING;

EID: 0034822910     PISSN: None     EISSN: None     Source Type: Journal    
DOI: 10.1109/IMTC.2001.928812     Document Type: Article

References (14)

1. Space compaction under generalized mergeability
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6. COMPACTEST: A method to generate compact test sets for combinatioinal circuits
7. A new framework for designing and analyzing BIST techniques and zero aliasing compression
8. Data compression technique for test responses
9. Testing computer hardware through compression in space and time
10. Reducing the MISR size
11. Synthesis of zero-aliasing elementary-tree space compactors